A reset is an operation used to force a system of chips comprising circuitry into a stable and known state. In order to reset a circuitry in a plurality of clock domains, an asynchronous reset pulse may be transmitted to each of the plurality of clock domains. The reset pulse is then synchronized to a clock of each of the plurality of clock domains before being used for resetting the circuitry in a respective clock domain.
The reset pulse in each particular clock domain may be held for several clock cycles for all circuitry in the particular clock domain to be reset. The resetting of a circuitry in a particular clock domain is independent of a resetting of a circuitry in another clock domain. Since the clock frequencies and the number of clock cycles needed for resetting circuitry for each clock domain are independent of those for another clock domain, determining which particular circuitry has completed the resetting first is difficult.
Moreover, when driving an asynchronous reset to a plurality of clock domains, the reset pulse may not meet recovery and removal timing requirements in one or more clock domains on either a rising edge or a falling edge of the asynchronous signal. Recovery time refers to a time between, when the reset is released (de-asserted) and a time when the clock signal is active (becomes high). Removal time refers to a time between, when the clock signal is active (becomes high) and the time when the reset is released (de-asserted). For example, the time requirements in a clock domain may not be satisfied if an asynchronous reset is released near an active edge of a flip-flop such that the output of the flip-flop becomes meta-stable. Failing to meet the timing requirement may result in the resetting operation for the particular domain being lost. An external logic may need to be aware of whether a resetting operation for a clock domain has concluded successfully. In addition, the external logic may need to know whether the reset operation has concluded for all the circuitry in the plurality of clock domains.